1. Field of the Invention
The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a three-electrode surface-discharge plasma display panel.
2. Description of the Related Art
FIG. 1 shows a structure of a general three-electrode surface-discharge plasma display panel, FIG. 2 shows an electrode line pattern of the panel shown in FIG. 1, and FIG. 3 shows an example of a pixel of the panel shown in FIG. 1. Referring to the drawings, address electrode lines A1, A2, . . . , Amxe2x88x921 and Am, dielectric layers 11 and 15, Y electrode lines Y1, . . . , and Yn, X electrode lines X1, . . . , and Xn, phosphors 16, partition walls 17 and a MgO protective film 12 are provided between front and rear glass substrates 10 and 13 of a general surface-discharge plasma display panel 1.
The address electrode lines A1, A2, . . . , Amxe2x88x921 and Am are coated over the front surface of the rear glass substrate 13 in a predetermined pattern. The lower dielectric layer 15 entirely coats the front surface of the address electrode lines A1, A2, . . . , Amxe2x88x921 and Am. The partition walls 17 on the front surface of the lower dielectric layer 15 are parallel to the address electrode lines A1, A2, . . . , Amxe2x88x921 and Am. The partition walls 17 define discharge areas of the respective pixels and prevent optical crosstalk among pixels. The phosphors 17 coat the partition walls 17.
The X electrode lines X1, . . . and Xn and the Y electrode lines Y1, . . . and Yn are arranged on the rear surface of the front glass substrate 10 and are orthogonal to the address electrode lines A1, A2, . . . , Amxe2x88x921 and Am in a predetermined pattern. The respective intersections define corresponding pixels. The X electrode lines X1, . . . and Xn and the Y electrode lines Y1, . . . and Yn each comprise conductive indium tin oxide (ITO) electrode lines (Xna and Yna of FIG. 3) and metal bus electrode lines (Xnb and Ynb of FIG. 3). The upper dielectric layer 11 entirely coats the rear surface of the X electrode lines X1, . . . and Xn and the Y electrode lines Y1, . . . and Yn. The MgO protective film 12 for protecting the panel 1 against strong electrical fields entirely coats over the rear surface of the upper dielectric layer 11. A gas for forming a plasma is hermetically sealed in a discharge space 14.
The above-described plasma display panel is basically driven such that a reset step, an address step and a sustain-discharge step are sequentially performed in a unit subfield. In the reset step, wall charges remaining in the previous subfield are erased and space charges are evenly formed. In the address step, the wall charges are formed in a selected pixel area. Also, in the sustain-discharge step, light is produced at the pixel at which the wall charges are formed in the address step. In other words, if alternating pulses of a relatively high voltage are applied between the X electrode lines X1, . . . and Xn and the Y electrode lines Y1, . . . and Yn, a surface discharge occurs at the pixels at which the wall charges are formed. Here, plasma is formed at the gas layer of the discharge space 14 and the phosphors 142 are excited by ultraviolet rays and thus emit light.
FIG. 4 shows the structure of a unit display period based on a driving method of a general plasma display panel. Here, a unit display period represents a frame in a progressive scanning method, and a field in the case of an interlaced scanning method. The driving method shown in FIG. 4 is generally referred to as a multiple address overlapping display driving method. According to this driving method, pulses for a display discharge are consistently applied to all X electrode lines X1, . . . and Xn and all Y electrode lines Y1, . . . and Yn, and pulses for resetting or addressing are applied between the respective pulses for a display discharge. Here, the pulses for resetting or addressing are applied to the Y electrode lines corresponding to a plurality of subfields SF1, . . . and SF8 set as driving periods for the purpose of displaying gray scales in a time-divisional manner.
Thus, compared to an address-display separation driving method, the multiple address overlapping display driving method has an enhanced display luminance. Here, the address-display separation driving method refers to a method in which, within a unit subfield, reset and address steps are performed for all Y electrode lines Y1, . . . and Yn, during a certain period and a display discharge step is then performed.
Referring to FIG. 4, a unit field or frame is divided into 8 subfields SF1, . . . and SF8 for achieving a time-divisional gray scale display. Also, in each subfield, reset, address and sustain-discharge steps are performed, and the time allocated to each sub-field is determined by the display discharge time corresponding to gray scales. For example, in the case of displaying 256 gray scales with 8-bit image data in units of frames, assuming that a unit frame, generally {fraction (1/60)} sec consists of 256 unit times, the first subfield SF1 driven by the image data of the least significant bit has 1 (2xc2x0) unit time, the second subfield SF2 2 (21) unit times, the third subfield SF3 4 (22) unit times, the fourth subfield SF4 8 (23) unit times, the fifth subfield SF5 16 (24) unit times, the sixth subfield SF6 32 (25) unit times, the seventh subfield SF7 64 (26) unit times, and the eighth subfield SF8 driven by the image data of the most significant bit 128 (27) unit time, respectively. In other words, since the sum of the unit times allocated to the respective subfields is 255 unit times, it is possible to achieve 255 gray scale display, and 256 gray scale display inclusive of one gray scale in which a no display discharge occurs at any subfield.
If an address step is performed for a Y electrode line and then a display discharge step is performed in the first subfield SF1, an address step is performed for the corresponding Y electrode line at the second subfield SF2. The same procedure is applied to subsequent subfields SF3, . . . and SF8. For example, if an address step is performed for a corresponding Y electrode line and then a display discharge step is performed in the seventh subfield SF7, an address step is performed for the corresponding Y electrode line at the eighth subfield SF8. Although the time for a unit subfield equals the time for a unit field or frame, the respective unit subfields are overlapped on the basis of driven Y electrode lines Y1, . . . and Y480 to form a unit field or frame. Thus, since all subfields SF1, . . . and SF8 exist at every timing, time slots for addressing, depending on the number of subfields, are set between the respective display discharge pulses for the purpose of performing the respective address steps.
As one of the above-described multiple address overlapping display driving methods, a driving method in which address steps are performed in the order of Y electrode lines corresponding to the respective subfields between pulses for each. display discharge, is generally used. In this driving method, conventionally, a constant voltage of pulses of display data signals are applied to the address electrode lines selected in accordance with the respective Y electrode lines scanned in the order of the respective subfields. However, since the scanning timings for the respective subfields are different, the standby times required for wall charges which have been formed on the respective Y electrode lines waiting for the pulses for the first display discharge, are different. As the standby time becomes longer, many more of the wall charges which have been formed at the pixels to be displayed are removed. Therefore, according to the conventional driving method, it is quite highly probable that only pixels to be displayed at subfields having the first scanning time slot, for example, the first subfield SF1 and the fifth subfield SF5, will be consistently displayed. Thus, uniformity and stability of a display may be deteriorated.
To solve the above problem, it is an object of the present invention to provide a method for driving a plasma display panel which can increase the uniformity and stability of a display by preventing a phenomenon in which a display discharge does not occur consistently at to-be-displayed pixels of a specific subfield.
Accordingly, to achieve the above object, there is provided a method for driving a plasma display panel having front and rear substrates opposed to and facing each other, X and Y electrode lines formed between the front and rear substrates to be parallel to each other and address electrode lines formed to be orthogonal to the X and Y electrode lines, to define corresponding pixels at interconnections, such that wherein a scan pulse is applied to the respective Y electrode lines with a predetermined time difference and the corresponding display data signals are simultaneously applied to the respective address electrode lines to form wall charges at pixels to be displayed and pluses for a display discharge are alternately applied to the X and Y electrode lines to cause a display discharge at the pixels where the wall charges have been formed. Here, the scan pulse is progressively applied between pulses for a display discharge, to the corresponding Y electrode lines of a plurality of subfields set as driving periods for time-divisional gray scale display, and the voltage of the display data signal applied to the pixels to be displayed as a time difference between the first pulse among the pulses for a display discharge and the pulse of the display data signal applied to the pixels to be displayed before application of the first pulse, becomes larger.
Therefore, since a phenomenon in which a display discharge does not occur consistently at to-be-displayed pixels of a specific subfield is prevented by a change in the scanning order of the respective subfields, the uniformity and stability of a display can be increased.